Senior ASIC Verification Engineer, System Verilog
One of our customers is looking for a ASIC verification engineer, System Verilog. This is a consulting assignment.
Role Description
The project scope is to develop new data networking equipment.
You will work with functional verification of a new ASIC.
You will work in a team together with designers and other verification engineers.
Position Details
Location: Stockholm
Start date: As soon as possible
Duration: 12 months
Competence/Experience – Mandatory
Experience from ASIC verification
Knowledge of System Verilog and VHDL
Experience from block level and sub-system level verification using UVM
English (verbal and writing)
Competence/Experience – Optional
Experience from working with Ethernet protocol
Experience from test bench modification / development
Experience from working with contstraind random methodology and test-vectors and assertions
Competence used in networking technology
Academic degree
Swedish (verbal and writing)
Personality
Good communication skills
Structured
Strong feeling for producing high quality work
Ability to work independently
Ability to work in teams
