ASIC VERIFICATION ENGINEER
ASIC Verification Engineer
Key Responsibilities
Lead and manage the end-to-end verification process for complex SoC (System-on-Chip) designs, ensuring compliance with functional specifications and industry standards.
Collaborate closely with design, architecture, and validation teams to define verification strategies and ensure seamless integration across functional blocks.
Develop comprehensive test plans and implement constrained-random, coverage-driven verification environments using SystemVerilog and UVM methodology.
Create and maintain automation scripts (e.g., Python, Perl, or TCL) to streamline regression execution, log analysis, and coverage reporting.
Drive functional and code coverage closure through metric tracking, gap analysis, and targeted test development.
Debug complex design and testbench issues in SoC environments, performing waveform analysis and root-cause investigations.
Mentor junior engineers on verification best practices, UVM testbench architecture, and debug methodologies.
Coordinate activities and maintain effective communication between onsite and offshore verification teams to ensure timely delivery.
Technical Skills & Tools
Verification Languages: SystemVerilog, UVM, Assertions (SVA)
Coverage: Functional coverage, code coverage, coverage closure strategies
Automation & Scripting: Python, Perl, Shell/TCL scripting for regression automation and productivity tools
Simulation & Debug Tools: VCS, Questa, Verdi, DVE, SimVision
Protocols: (Preferred) ARM processors, CHI interconnects, PCIe, DDR, AMBA (AXI/AHB/APB)
Version Control & CI/CD: Git, Jenkins, regression dashboard integration
EDA Tools: Synopsys, Cadence, Mentor Graphics suites
Preferred Experience
Exposure to ARM processor subsystems and CHI protocols.
Hands-on verification experience with PCIe or DDR interfaces.
Familiarity with low-power verification, clock/power domain crossing checks, and formal verification.
